System memory is typically arranged in the form of multiple memory banks. Consecutive read or write accesses to an address or addresses of one of the banks (i.e., consecutive memory accesses to the system memory directed to the same rank, same bank, but different pages) is referred to as a “memory bank conflict.” Memory bank conflicts result in performance penalties due to latency, pre-access processes (e.g., pre-access charge processes), and the inability for parallel memory access and address decoding processes. This is especially true for Phase Change Memory devices, which have (relatively) long access times and thus suffer a greater performance penalty than other memory devices.
Current solutions for reducing the effects of bank conflicts are based on rearranging memory accesses in the event of a bank conflict—e.g., deferring the lowest priority memory access in the event of a bank conflict. These solutions are slow and require logic or modules to re-arrange memory access transactions on the fly. What is needed is a solution to reduce the likelihood of memory bank conflicts, and thus eliminate the need to defer or re-arrange memory access transactions.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.